1. Field of the Invention
The present invention relates to a data transfer apparatus and a data transfer method using a packet.
2. Description of the Related Art
Technologies for data transfer using a packet have been adopted in various fields. Transmission Control Protocol/Internet Protocol (TCP/IP) is a technology to transfer data on the Internet on a packet basis. Peripheral Component Interconnect-Express (PCI-Express) is a technology to transfer data between integrated circuits on a packet basis. Further, Network On Chip (NoC) is another technology to transfer data within an integrated circuit on a packet basis.
Data transfer on a packet basis has an advantage in that various pieces of information such as address and data essential for transfer can be transferred using a small number of signal lines. For example, in PCI-Express, only two pairs of differential lines are necessary for data transfer. Data transfer on a packet basis has another advantage in that transfer rate can be easily raised. The data transfer system on a packet basis, more cycles required for transfer compared to non-packet basis data transfer systems. Thus, technologies have been discussed to increase efficiency in data transfer on a packet basis in which a packet configuration is improved to reduce an amount of information to transfer so that the number of cycles required for transfer is decreased.
As a measure to decrease information to transfer, PCI-Express described in “PCI Express Base Specification Revision 1.1” PCI-SIG, March 2005 describes a protocol in which the data except the head 4-byte data and the tail 4-byte data in a data payload at memory request is handled as valid, and the portion in a packet configuration except the byte enable identification information (Last DW BE 1st DW BE) corresponding to the head 4-byte data and the tail 4-byte data of the data payload is omitted, so that the information on the packet is decreased.
Japanese Patent Application Laid-Open No. 11-102341 discusses a data transfer system in which only valid data is transferred based on byte enables attached, in units of bytes, to data to transfer onto a serial bus, so that transfer of invalid data is suppressed and efficiency in data transfer is enhanced.
Meanwhile, a parallel bus in non-packet basis is mainly used for data transfer within an integrated circuit. A protocol in a parallel bus within an integrated circuit often includes byte enables (e.g., 8 bits) for every unit of data (e.g., 64 bits that is equal to a bus width) to indicate which data byte is valid in one unit of data transfer (e.g., 64 byte=64-bit bus width×8 burst transfer). Similarly, protocols on data transfer for Dynamic Random Access Memory (DRAM) as a mainstream storage apparatus also support use of the byte enables. In such protocols, data transfer from a master to a slave (e.g., DRAM) in a whole system including within an integrated circuit and between integrated circuits is achieved by mutual use of transfer on packet basis or transfer in non-packet basis with use of byte enables.
With respect to a transfer path from a parallel bus within an integrated circuit to PCI-Express between integrated circuits, a case where data of one transfer unit from a parallel bus contains invalid data other than the head 4 byte and the tail 4 byte thereof is described in detail. A protocol in PCI-Express handles the data except tail and head portions in a data payload (i.e., one transfer unit) as valid data to transfer, and thereby at data transfer to PCI-Express, the transfer is divided at a position in invalid data at least, and headers need to be added to the divided transfers respectively. For example, when data is transferred to PCI-Express, the data being transferred from a parallel bus of 64-bit data bus width as one unit of 64 byte (64 bit bus width×8 burst transfer) containing invalid data of 1 byte at every 8-byte data, the data is divided into 8-byte transfers for example, and the transfers each need to have a header. This division and increased headers occupy the transfer bandwidth, and impairs transfer efficiency.
On the contrary, in the case with Japanese Patent Application Laid-Open No. 11-102341, a byte enable is attached to data, in units of bytes, to be transferred onto a serial bus, and thereby when the data contains valid data at high rate, the high amount of byte enable data itself impairs the transfer efficiency.